The items of literature referenced in this specification are listed below, and they will be referenced by reference number. [Reference 2]: K. Itoh, IEEE Journal of Solid State Circuit, Vol. 25, No. 3, (1990), pp. 778-789 ([Reference 2] is the original work referenced in [Reference 1]).
[Reference 1] discusses noise arising via word lines when a dynamic random access memory (DRAM) is subjected to amplification. It further discusses, as a case of noise arising via word lines, the phenomenon that a noise voltage on an unselected word line attributable to the coupling capacitance of data lines and the word line gives rise to noise on paired data lines. The impact of that noise is dependent on the structure of the paired data lines (whether an open data line structure or a folded data line structure) and the data line precharging system (whether a VD precharging system or a VD/2 precharging system). As a conclusion, it is stated that the use of a folded data line structure and a VD/2 precharging system helps reduce the noise.
The inventors pertaining to the present application for patent, before filing the application, studied in detail the occurrence of noise attributable to the structure of a 1 Gb DRAM array using micro fabrication technology of 0.16 to 0.13 .mu.m and the coupling capacitance of data lines and word lines. FIG. 10A illustrates a planar layout of the DRAM array studied before this application, and FIG. 10B illustrated part of a corresponding circuit diagram. In the planar layout of FIG. 10A, memory cells (MCs) are disposed at prescribed intersections of data lines (DLs) and word line (WLs). This data line structure is a so-called folded data line structure. Here are shown only the DLs for reading signals out of memory cells, the WLs serving as gates for selecting transistors, regions of diffused layer (ACTs), data line contacts (DLCTs) for connecting ACTs and DLs, and storage node contacts (SNCTs) for connecting ACTs and storage nodes of capacitors, but the storage nodes connected to the SNCTs are not shown. Above and underneath the memory array are arranged an upper subword driver array (SWDA-U) and a lower subword driver array (SWDA-D), and two word lines WLs are alternately connected to the upper and lower subword driver arrays. "Subword driver" will be abbreviated to SWD below as required. To the left and right of the memory array are disposed a left sense amplifier array (SAA-L) and a right sense amplifier array (SAA-R), respectively, and two data lines DLs are alternately connected to the left and right sense amplifier arrays. "Sense amplifier" will be abbreviated to SA below as required.
These alternate arrangements of SWDs and SAs are intended to ease the tightness of their layout pitches. To look at the boundary between the SWDA-U and the memory array, for instance, there is seen a reiterated pattern of two WLs, each passing the boundary and entering the SWD (WL0, WL1, WL4 and WL5), and ones ending at the boundary (WL2, WL3, WL6 and WL7). Connection of WLs to the SWD in this manner makes possible easing of the layout pitch per SWD in the direction of data lines to an equivalent of two WLs. For the layout of the SAs as well, the alternate arrangement serves to ease the pitch in the direction of word lines to two pairs of DLs (four DLs). Since memory cells are extremely small in a DRAM, the pitches of WLs and DLs are very fine. This means increased difficulty in laying out SWDs and SAs at prescribed pitches, and accordingly the alternate arrangement can make an important contribution.
Now to look at the relationships of connection between the WLs and the SWD arrays, and more specifically to two mutually adjoining memory cells MC0 and MC1 which are connected to the DL0T, both the WL0 and the WL1 connected to these cells are connected to the SWDA-U. On the other hand, to look at two other mutually adjoining memory cells MC2 and MC3 connected to the DL0B, they also share the same DLCT, and both the WL2 and the WL3 connected to these cells are connected to the SWDA-D. Therefore, in the layout of the memory array of FIGS. 10A and 10B, the WLs connected to the two memory cells sharing the DLCT are connected to the same SWD array. In an overall view of the memory array, as the pattern shown in FIG. 10A is reiterated vertically and horizontally, all the WLs connected to the MCs connected to the DL0T (WL0, WL1, WL4 and WL5 in the diagram) are connected to the SWDA-U, and all the WLs connected to the MCs connected to the DL0B (WL2, WL3, WL6 and WL7 in the diagram) are connected to the SWDA-D. Accordingly all the word lines connected to memory cells connected to any one data line are connected to the same subword driver array.
These relationships are represented in a circuit diagram which is presented as FIG. 10B. In a folded data line structure, memory cells are connected to half of the intersections between data lines and word lines. For instance, while the memory cell MC0 is connected between the DL0T and the WL0, no MC is connected between the DL0B and the WL0. An MC consists of a selecting transistor TG and a cell capacitor CS. One of the electrodes of the CS is a plate PL, which is connected in common with other memory cells in the array. The other electrode of the CS is connected to either one of the source or the drain of the TG, and the other of the drain or the source of the TG is connected to the DL. The DL0T and the DL0B are paired and connected to the SA0 in the SAA-L, and the DL1T and the DL1B are connected to the SA1 in the SAA-R. These SAs amplify a very small voltage difference generated between paired DLs by a signal from the memory cell to a higher level for one DL and to a lower level for the other DL.
Only the parts of MC0, MC1, MC2 and MC3 of FIGS. 10A and 10B are enlarged, with their enlarged layout shown in FIG. 11A and their circuit diagram in FIG. 11B. Parasitic capacitors emerging between the WLs and DLs of these MCs are also shown. Between the WL0 or WL1 and the DL0T arises a parasitic capacitance C00 or C01, respectively. Between the WL0 or WL1 and the DL0B arises a parasitic capacitance C00B or C01B, respectively. Between the WL2 or WL3 and the DL0B arises a parasitic capacitance C02 or C03, respectively. Between the WL2 or WL3 and the DL0T arises a parasitic capacitance C02B or C03B, respectively.
Cross sections A-A', B-B' and C-C' of the parts pointed by arrows in the layout of FIG. 11A are respectively illustrated in FIGS. 12A, B and C. The cross sections in FIGS. 12A-12C refer to areas near the two word lines WL0 and WL1 in the direction represented by arrows in FIG. 11A. The ACT region on the substrate is the active region of the MOS transistor, while other parts on the substrate are device isolation regions. Over them are wired WLs and DLs, and the DLs are connected to ACTs by oval DLCTs. SNs are storage nodes of cell capacitors CSs, and connected to the ACTs by SNCTs. The upper electrodes PLs of the CSs are commonly connected by cells in the array, and over them are arranged two-layered metallic wires M2 and M3.
To compare C00 and C00B here, as shown in the cross section A-A' of FIG. 12A, the DLCT0 connected to the DL0T passes between the WL0 and the WL1 very close to them. The distance between the DLCT0 and the WL0, where the memory cell is made by micro fabrication, is about 30 nm. Therefore, the C00, which is a capacitance between the DL0T and the WL0, is substantially determined by the part between the DL0T and the WL0.
On the other hand, as shown in the cross section B-B' of FIG. 12B, the DL0B merely passes above the WL0, and the C00B, which is the capacitance between the DL0B and the WL0, is determined by the interlayer distance between the DL and the WL, and is about 250 nm in the 0.13 .mu.m generation. Therefore, the C00B is far smaller than the C00; a detailed capacitance simulation has revealed that the C00B is about 1% against a C00 of 100%. Thus, as illustrated in FIG. 11B, in a folded data line structure, although the coupling capacitance of the WL0 with respect to the DL0T and the DL0B may appear balanced between the C00 and the C00B, the C00 is predominantly great in a large scale integrated DRAM using small memory cells, resulting in an imbalance. Similarly, the C01, C02 and C03 are far greater than the C01B, C02B and C03B, respectively. In other words, the DL-WL coupling capacitance is great in the presence of an MC between the DL and the WL, but negligibly small in its absence.
This imbalance in DL-WL coupling capacitance is a new problem which has become actualized by the decrease in the thickness of the insulating film parallel to the substrate relative to the thickness of the interlayer insulating film in the direction normal to the substrate, which in turn has resulted from the large scale integration of the DRAM. In a memory array in which the DL-WL coupling capacitance is unbalanced, WL noise poses a problem as will be described below.
FIG. 13 illustrates the memory array of FIG. 10B and a data pattern in a case wherein the word line noise reaches its peak. The WL0 through the WL7 are connected to the SWD0 through the SWD7, respectively; the SWD0, SWD1, SWD4 and SWD5 are arranged in the SWDA-U; and the SWD2, SWD3, SWD6 and SWD7 are arranged in the SWDA-D. The DL0T and DL0B are connected to the SA0 in the SAA-L, and the DL1T and DL1B are connected to the SA1 in the SAA-R. The circuit diagram of the SAs is presented as FIG. 14A, and the operating wave forms of the array are shown in FIG. 14B.
Now is considered with reference to FIG. 13 a case in which the WL0 is selected. Other WLs than the WL0 in the array are connected to either a VSSU or a VSSD by an N-channel MOS transistor in the SWD. As illustrated in FIG. 14B, every SWD's output is 0 V during standby. In each MC, the selecting transistor is turned off, and a voltage of VDL (e.g. 1.8 V) or VSS (e.g. 0 V) is written into the capacitor according to information. In each SA, the SHRU and SHRD are at VPP (e.g. 3.5 V), the CS and CSN are at VBLR (e.g. 0.9 V), the BLEQ is at VPP, and the YS is 0 V, while the DL is precharged to a potential of VBLR.
When a bank activate command and an address are entered into the DRAM, if the memory array illustrated here is selected, the SHRL and BLEQ will be reduced to 0 V, and the precharging is interrupted, followed by the activation of the WL0 to 3.5 V in the SWD0. Then the selecting transistor of the MC leading to the WL0 is turned on, and signals emerge from the cell capacitor to the DL0, DL1 and so forth. It is supposed now that low level (L) signals appear to all the 1024 pairs or 2048 units of T side DLs from DL0T through DL1023T except the DLnT, and a high level (H) signal appears only to the DLnT. Then, since no signals emerge to the other DLs, from DL0B through DL1023B, they remain at 0.9 V. This pattern, or a pattern inverted with respect to H and L, is the worst condition in which the WL noise is at its greatest. Then, as the SA is activated by driving the CSN to 0 V and the CSP to 1.8 V, all the DLs from DL0T through DL1023T except DLnT are amplified to 0 V, and all the DLs from DL0B to DL1023B except DLnB are amplified to 1.8 V.
How this takes place is illustrated in FIG. 13. The circled Ls above the DL0T and the DL1T indicated that the DL0T and the DL1T are amplified to 0 V, and the circled Hs above the DL0B and the DL1B indicate that the DL0B and the DL1B are amplified to 1.8 V. The noise then arising on the WL0 will be as follows. The WL0 receives negative noise from the data lines from DL0T through DL1023T other than the DLnT via a coupling capacitance. On the other hand, the WL0 receives positive noise from the data lines from DL0B through DL1023B other than the DLnB via a coupling capacitance. Whereas the noise arising on the WL0 will be the sum of these noise components, since the WL0 is connected to the MC which in turn is connected to the T side DLs from DL0T through DL1023T as stated above, the WL0-DL0B coupling capacitance, for instance, is only about 1% of the WL0-DL0T coupling capacitance. Thus, the coupling capacitance between the WL0 and data lines on the B side is negligibly smaller than the coupling capacitance of data lines between the WL0 and the T side. Therefore, the negative noise arises almost uncanceled on the WL0. This is indicated by the circled minus signs above the WL0. Similarly, negative noise arises on the WL1, WL4 and WL5. Conversely, as the WL2, WL3, WL6 and WL7 are connected to the MC which in turn is connected to the B side DLs from DL0B through DL1023B, the WL2-DL0T coupling capacitance, for instance, is smaller than, only about 1% of, the WL0-DL0B coupling capacitance. Thus, the coupling capacitance between the WL2 and data lines on the T side is negligibly smaller than the coupling capacitance between the WL2 and data lines on the B side. Therefore, positive noise arises on these WLs, which is indicated by the circled plus signs above the WLs. In the waveform of FIG. 14(b) as well, WL noise on the WL0, WL1 and WL2 is represented.
The noise having arisen here on the WLs will flow as an electric charge to the VSS wires over the SWD through the channel MOS transistor in the SWD. As this VSS wiring in a DRAM extends for a few millimeters over the SWD from a bonding pad for voltage source in the middle of the chip to an end of the chip, it has a high impedance. Therefore, the noise having arisen on a word line emerges as it is in the VSS on the SWD.
While this WL noise is positive on one half of all the WLs of the array and negative on the other half, the alternate connection of WLs to two SWDs in the array of FIG. 13 results in the occurrence of negative noise on every WL connected to the SWDA-U and of positive noise on every WL connected to the SWDA-D. Therefore, the negative noise components having arisen on the VSSU, which is the VSS wiring on the SWDA-U, reinforce one another, and the positive noise components having arisen on the VSSD, which is the VSS wiring on the SWDA-D, also reinforce one another. Accordingly these noise aggregates are very great. A detailed circuit simulation has revealed that they are about 100 mV each. Furthermore, noise components having arisen on WLs take a long time to attenuate because they are not canceled until they reach the bonding pad for voltage source in the middle of the chip.
This WL noise occurring during DL amplification returns to the DLs via the WL-DL coupling capacitance, and invites erroneous actions. When an H level signal emerges only on the DLnT as shown in FIG. 13, negative noise components from the WL0, WL1, WL4, WL5 and so forth return to the DLnT. Also, positive noise components from the WL2, WL3, WL6, WL7 and so forth return from the DLnB. Thus, as viewed from the DLn pairs, noise in the reverse direction to the desired signals return to reduce the quantity of signals. If the electric charge stored in the cell capacitor of the memory cell at the intersection between the WL0 and the DLnT has been reduced by a leak or otherwise, there will be less of H level signals emerging at the DLnT when the WL0 is activated, so that this WL noise will invert the data at the time of amplification. How this occurs is illustrated in FIG. 14B; the DLnT and DLnB are amplified in the direction reverse to the minute difference in potential having arisen on the DLnT and DLnB at the time of WL activation, inviting erroneous reading of data.
Thus, in the memory array of FIGS. 10A-10B studied before this application for patent, as the WL noise components on word lines work in a direction of reinforcing one another in the sense amplifier driver SWD in the worst case, there is the problem of increased WL noise. This deteriorates the signal read out by the sense amplifier, and accordingly destabilizes the operation of the memory.
Therefore, an object of the present invention is to provide a highly reliable memory array by reducing the noise arising on word lines when data lines are subjected to amplification in a large scale integrated DRAM in pursuit of micro fabrication.